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| HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 256 MBit Synchronous Low-Power DRAM Data Sheet Revision Dec. 2002 Features * Automatic and Controlled Precharge Command -7.5 -8 125 8 6 9.5 6 Units MHz ns ns ns ns 133 7.5 5.4 9.5 6 * Programmable Burst Length: 1, 2, 4, 8 and full page * Data Mask for byte control * Auto Refresh (CBR) * 8192 Refresh Cycles / 64ms * Very low Self Refresh current * Power Down and Clock Suspend Mode fCK,MAX tCK3,MIN tAC3,MAX tCK2,MIN tAC2,MAX * 16Mbit x16 organisation * VDD = VDDQ = 3.3 V * Fully Synchronous to Positive Clock Edge * Four Banks controlled by BA0 & BA1 * Programmable CAS Latency: 2, 3 * Programmable Wrap Sequence: Sequential or Interleave * Random Column Address every CLK (1-N Rule) * P-TFBGA-54, with 9 x 6 ball array with 3 depopulated rows, 12 x 8 mm2 * P-TSOPII-54 alternate package * Operating Temperature Range Commerical (00 to 700 C) Description The HYB 39L256160AC Mobile-RAM is a new generation of low power, four bank Synchronous DRAM's organized as 4 banks x 4Mbit x 16. These synchronous Mobile-RAMs achieve high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. The device operates with a single 3.3V 0.3V power supply. Compared to conventional SDRAM the self-refresh current is further reduced. The Mobile-RAM devices are available in FBGA "chip-size" or TSOPII packages. INFINEON Technologies AG 1 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Ordering Information Type HYB 39L256160AC-8 HYB 39L256160AT-7.5 HYB 39L256160AT-8 Function Code Package PC100-222-620 BGA-BOC Description 133 MHz 4B 4M x16 LP-SDRAM 100 MHz 4B 4M x16 LP-SDRAM HYB 39L256160AC-7.5 PC133-333-522 BGA-BOC PC133-333-522 P-TSOP-54 (400mil) 133 MHz 4B 4M x16 LP-SDRAM PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B 4M x16 LP-SDRAM Pin Definitions and Functions CLK CKE CS RAS CAS WE A0 - A12, A0 - A8 BA0, BA1 Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Row Addresses Column Addresses Bank Select DQ LDQM, UDQM Data Input/Output Data Mask Power (+ 3.3V) Ground Power for DQ's (+3.3V) Ground for DQ's Not connected VDD VSS VDDQ VSSQ N.C. INFINEON Technologies AG 2 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Pin Configuration for BGA devices 1 2 3 7 8 9 VSS DQ14 DQ15 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A VDDQ VSSQ VDDQ VSSQ VDD CAS BA0 A0 DQ0 VDD DQ1 DQ13 B DQ2 DQ12 DQ11 C DQ4 DQ3 DQ10 DQ9 D DQ6 DQ5 DQ8 NC E LDQM DQ7 UDQM A12 A8 CLK A11 A7 F G H RAS BA1 A1 WE CS A10 VSS A5 A4 J A3 A2 VDD < Top-view > INFINEON Technologies AG 3 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Pin Configuration for TSOP devices 16Mb x 8 M x 1616 16 M x 8 32 M x 4 VDD DQ0 VDD DQ0 VDD N.C. VDDQ DQ1 DQ2 VDDQ N.C. DQ1 VDDQ N.C. DQ0 VSSQ DQ3 DQ4 VSSQ N.C. DQ2 VSSQ N.C. N.C. VDDQ DQ5 DQ6 VDDQ N.C. DQ3 VDDQ N.C. DQ1 VSSQ DQ7 VSSQ N.C. VSSQ N.C. VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD N.C. WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD N.C. WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD VDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS N.C. VSS DQ7 VSS DQ15 VSSQ N.C. DQ3 VSSQ N.C. DQ6 VSSQ DQ14 DQ13 VDDQ N.C. N.C. VDDQ N.C. DQ5 VDDQ DQ12 DQ11 VSSQ N.C. DQ2 VSSQ N.C. DQ4 VSSQ DQ10 DQ9 VDDQ N.C. VDDQ N.C. VDDQ DQ8 VSS N.C. DQM CLK CKE N.C. A11 A9 A8 A7 A6 A5 A4 VSS N.C. DQM CLK CKE N.C. A11 A9 A8 A7 A6 A5 A4 VSS N.C. UDQM CLK CKE A12 N.C. A11 A9 A8 A7 A6 A5 A4 VSS VSS VSS TSOPII-54 (10.16 mm x 22.22 mm, 0.8 mm pitch) SPP04121 INFINEON Technologies AG 4 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Functional Block Diagrams Column Addresses A0 - A8, AP, BA0, BA1 Row Addresses A0 - A12, BA0, BA1 Column Address Counter Column Address Buffer Row Address Buffer Refresh Counter Row Decoder Row Decoder Row Decoder Row Decoder Column Decoder Sense amplifier & I(O) Bus Column Decoder Sense amplifier & I(O) Bus Column Decoder Sense amplifier & I(O) Bus Memory Array Memory Array Memory Array Column Decoder Sense amplifier & I(O) Bus Memory Array Bank 0 8192 x 512 x 16 Bit Bank 1 8192 x 512 x 16 Bit Bank 2 8192 x 512 x 16 Bit Bank 3 8192 x 512 x 16 Bit Input Buffer Output Buffer Control Logic & Timing Generator DQ0 - DQ15 Block Diagram: 16Mb x16 SDRAM (13 / 9 / 2 addressing) INFINEON Technologies AG 5 CLK CKE CS RAS CAS WE DQMU DQML SPB04124 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Signal Pin Description Pin CLK CKE Type Input Input Signal Polarity Function Pulse Level Positive The system clock input. All of the SDRAM inputs are Edge sampled on the rising edge of the clock. Active High Active Low Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Pulse CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. During a Bank Activate command cycle, A0 - A12 define the row address (RA0 - RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An define the column address (CA0 - CAn) when sampled at the rising clock edge. CAn depends from the SDRAM organization: 16M x16 SDRAM CA0 - CA8 (Page Length: 512bits) RAS CAS WE A0 - A12 Input Pulse Active Low Input Level - In addition to the column address, A10 (=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input DQx Level - - Bank Select Inputs. Selects which bank is to be active. Data Input/Output pins operate in the same manner as on conventional DRAMs. Input Level Output INFINEON Technologies AG 6 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Pin LDQM UDQM, Type Input Signal Polarity Function Pulse Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, L/UDQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. LDQM and UDQM controls the lower and upper bytes in x16 SDRAM. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. VDD VSS VDDQ VSSQ Supply - Supply - - - INFINEON Technologies AG 7 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and xDQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Operation Bank Active Bank Precharge Precharge All Write Read Mode Register Set4 No Operation Burst Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Clock Suspend Entry Clock Suspend Exit Power Down Entry (Precharge standby or active standby) Power Down Exit Device State CKEn-1 CKEn DQM BA0 BA1 AP= A10 Addr CS L L L L L L L L L L H L L H L X X H L RAS L L L H H H H L H H X L L X H X X X H X H X X CAS H H H L L L L L H H X L L X H X X X H X H X X WE H L L L L H H L H L X H H X X X X X H X L X X Idle3 Any Any Active3 Active Idle Any Active Any Idle Idle Self Refresh Active5 Active Idle Active5 Any Power Down 3 H H H H H H H H H H H H H L H L H X X X X X X X X X X X H L H L H L X X X X X X X X X X X X X X X X X V V X V V V V V X X X X X X X X X V L H L H L H V X X X X X X X X X V X X V V V V V X X X X X X X X X Write with Autoprecharge Active3 Read with Autoprecharge Active3 L H X X X X H L Data Write/Output Enable Active Data Write/Output Disable Active H H X X L H X X X X X X X X Notes 1. V = Valid, x = Don't Care, L = Low Level, H = High Level. 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BA0, BA1 signals. 4. Address Input for Mode Set (Mode Register Operation) 5. Power Down Mode can not be entered during a burst cycle. When this command is asserted during a burst cycle the device enters Clock Suspend Mode. INFINEON Technologies AG 8 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Mode Register Table BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) 0 0 Operation Mode CAS Latency BT Burst Length Mode Register (Mx) Operation Mode BA1 BA0 M12 M11 M10 M9 0 0 0 0 0 0 0 0 0 0 0 1 M8 0 0 M7 0 0 Mode Burst Read/ Burst Write Burst Read/ Single Write Burst Type M3 0 1 Type Sequential Interleave CAS Latency M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 Reserved Latency Reserved Reserved 2 3 Reserved Burst Length M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 full page 1 2 4 8 Reserved Reserved Length Sequential Interleave 1 2 4 8 INFINEON Technologies AG 9 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Power-On and Initialization The default power-on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. VDD must be applied before or at the same time as VDDQ to the specified voltage when the input signals are held in the "NOP" or "DESELECT" state. The power on voltage must not exceed VDD +0.3V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200ms is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register The Mode Register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), and a CAS Latency Field to set the access time at clock cycle, an The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. BA0 and BA1 have to be set to "0" to enter the Mode Register. Read and Write Operation When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 133MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is `2', then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation do not self terminate once the burst length has been reached. In other words, unlike burst length of 2, 4 and 8, full page burst continues until it is terminated using another command. INFINEON Technologies AG 10 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Similar to the page mode of conventional DRAM's, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be performed between different pages. When the partial array activation is set, data will get lost when self-refresh is used in all non activated banks. Burst Length and Sequence Burst Length 2 4 Starting Address (A2 A1 A0) xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 nnn 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 8 Full Page Refresh Mode Cn, Cn+1, Cn+2 not supported Mobile-RAM has two refresh modes, Auto Refresh and Self Refresh. Auto-Refresh Auto Refresh is similar to the CAS-before-RAS refresh of earlier DRAMs. All banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses. No bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock edge. The mode restores word line after the refresh and no external precharge INFINEON Technologies AG 11 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. In Auto-Refresh mode all banks are refreshed, independed if the partial activation has been set. Self-Refresh The chip has an on-chip timer that is used when the Self Refresh mode is entered. The self-refresh command is asserted with RAS, CAS, and CKE low and WE high at a clock edge. All external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any command. After self refresh exit an autorefresh command is recommended due to the chance of an exit just before the next internal refresh is executed. DQM Function DQMx has two functions for data I/O read and write operations. During reads, when it turns to "high" at a clock edge, data outputs are disabled and become high impedance after two clock periods (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Suspend Mode During normal access, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged before the Mobile-RAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all receiver circuits except for CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tREF) of the device. Exit from this mode is performed by taking CKE "high". One clock delay is required for power down mode entry and exit. Auto Precharge Two methods are available to precharge Mobile-RAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The Mobile-RAM automatically enters the precharge operation after tWR (Write recovery time) following the last data in. INFINEON Technologies AG 12 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Precharge Command There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock edge, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay tWR from the last data out to apply the precharge command. Bank Selection by Address Bits A10 0 0 0 0 1 BA0 0 0 1 1 x BA1 0 1 0 1 x Bank 0 Bank 1 Bank 2 Bank 3 all Banks Burst Termination Once a burst read or write operation has been initiated, there are several methods used to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, using a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. INFINEON Technologies AG 13 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Electrical Characteristics Absolute Maximum Ratings Operating Case Temperature Range (commercial) ....................................................... 0 to +70C Storage Temperature Range ................................................................................... -55 to +150C Input/Output Voltage VIN, VOUT ......................................................................... -1.0 to VDD + 0.5V Input/Output Voltage VIN, VOUT ................................................................................. -1.0 to +4.6V Power Supply Voltages VDD, VDDQ ............................................................................ -1.0 to +4.6V Power Dissipation ................................................................................................................... 0.7W Data out Current (short circuit) .............................................................................................. 50mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operation and DC Characteristics TCASE = 0 to 70C (commercial), VSS = 0V Parameter DRAM Core Supply Voltage I/O Supply Voltage Input High Voltage (CMD, Addr.) Input Low Voltage (CMD, Addr.) Data Input High (Logic 1) Voltage Data Input Low (Logic 0) Voltage Data Output High (Logic 1) Voltage Data Output Low (Logic 0) Voltage Input Leakage Current, any input (0V < VIN < VDDQ, all other inputs = 0V) Output Leakage Current (DQ is disabled, 0 V < VOUT < VDD) Notes 1. All voltages are referenced to VSS. 2. VIH may overshoot to VDDQ +2.0V for pulse width of <4ns with VDDQ =3.3V. VIL may undershoot to -2.0V for pulse width <4.0ns with VDDQ =3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. Symbol min. Limit Values max. 3.6 3.6 + 0.3 + 0.3 - 0.2 5 5 2.7 2.7 2.0 - 0.3 2.0 - 0.3 2.4 - -5 -5 Unit Notes V V 1, 2 1, 2 VDD VDDQ VIH VIL VIH VIL VOH VOL II(L) IO(L) VDDQ +0.3 V V V V V VDDQ +0.3 V IOH = -0.1mA IOL =-0.1mA mA mA INFINEON Technologies AG 14 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Capacitance TCASE = 0 to 70 C (commercial), f = 1 MHz Parameter Input Capacitance (CLK) Input Capacitance (A0 - A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) Input/Output Capacitance (DQ) Symbol Values min. max. 3.5 3.8 6.0 pF pF pF Unit CI1 CI2 CIO Operating Currents TCASE = 0 to 70 C (commercial) (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Operating current single bank access cycles Precharge standby current in Power Down Mode Precharge standby current in Non Power Down Mode No operating current tRC = tRC,MIN Symbol -7.5 max. 65 0.6 -8 max. 60 0.5 mA mA 3 3 Unit Note IDD1 IDD2P CS = VIH,MIN, CKE VIL,MAX CS = VIH,MIN, CKE VIH,MIN CKE VIH,MIN CKE VIL,MAX IDD2N IDD3N IDD3P IDD4 20 25 3.5 80 155 475 18 20 3.5 60 140 475 mA mA mA mA mA 3 3 3 3, 4 tCK = tCK,MIN, CS = VIH,MIN, active state (max. 4 banks) Burst Operating Current Read command cycling Auto Refresh Current Auto Refresh command cycling Self refresh current Notes tRC = tRC,MIN IDD5 IDD6 tCK =infinity mA 3. These parameters depend on the frequency. These values are measured at 133MHz for -7.5 and at 100MHz for -8 parts. Input signals are changed once during tCK. If the devices are operating at a frequency less than the maximum operation frequency, these current values are reduced. 4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 is used and the VDDQ current is excluded. INFINEON Technologies AG 15 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM AC Characteristics 1, 2 TCASE = 0 to 70 C (commercial), (Recommended Operating Conditions unless otherwise noted) Parameter Symbol -7.5 Values -8 min. max. min. max. Clock and Clock Enable Clock Cycle Time - Unit Note CAS Latency = 3 tCK3 CAS Latency = 2 tCK2 Clock frequency 7.5 9.5 - - - - 2.5 2.5 0.3 - - 133 105 5.4 6 - - 1.2 8 9.5 - - - - 3 3 0.5 - - 125 105 6 6 - - 1.5 ns ns - MHz MHz 2, 3, 6 CAS Latency = 3 fCK3 CAS Latency = 2 fCK2 Access Time from Clock CAS Latency = 3 tAC3 CAS Latency = 2 tAC2 Clock High Pulse Width Clock Low Pulse Width Transition Time Setup and Hold Times Input Setup Time Input Hold Time CKE Setup Time CKE Hold Time Mode Register Set-up Time Power Down Mode Entry Time Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time ns ns ns ns ns - - - tCH tCL tT tIS tIH tCKS tCKH tRSC tSB 1.5 0.8 1.5 0.8 2 0 - - - - - 7.5 2 1 2 1 2 0 - - - - - 8 ns ns ns ns CLK ns 4 4 4 4 - - tRCD tRP tRAS tRC tRRD tCCD 19 19 45 67 15 1 - - 100k - - - 19 19 48 70 16 1 - - 100k - - - ns ns ns ns ns CLK 5 5 5 5 5 Activate(a) to Activate(b) Command Period CAS(a) to CAS(b) Command Period Refresh Cycle INFINEON Technologies AG - 16 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM AC Characteristics (cont'd)1, 2 TCASE = 0 to 70 C (commercial), (Recommended Operating Conditions unless otherwise noted) Parameter Symbol -7.5 Refresh Period (8192 cycles) Self Refresh Exit Time Read Cycle Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency Write Cycle Write Recovery Time DQM Write Mask Latency Values -8 - 1 64 - ms CLK - min. max. min. max. Unit Note tREF tSREX - 1 64 - tOH tLZ tHZ tDQZ 3 1 3 - - - 7 2 3 0 3 - - - 8 2 ns ns ns CLK 2, 5, 6 - - - tWR tDQW 14 0 - - 14 0 - - ns CLK 7 - INFINEON Technologies AG 17 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Notes 1. For proper power-up see the operation section of this data sheet. 2. AC timing tests are referenced to the 0.9V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit (details will be defined later). Specified tAC and tOH parameters are measured with a 30pF only, without any resistive termination and with a input signal of 1V/ns edge rate. I/O 30 pF Measurement conditions for tAC and tOH 3. If clock rising time is longer than 1 ns, a time (tT /2 - 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) 6. Access time from clock tAC is 4.6ns for -7.5 components with no termination and 0pF load, Data out hold time tOH is 1.8ns for -7.5 components with no termination and 0pF load. 7. The write recovery time of tWR = 14ns cycles allows the use of one clock cycle for the write recovery time when the memory operation frequency is equal or less than 72MHz. For all memory operation frequencies higher than 72MHz two clock cycles for tWR are mandatory. INFINEON recommends to use two clock cylces for the write recovery time in all applications. INFINEON Technologies AG 18 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Timing Diagrams 1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. AC- Parameters 8.1 AC Parameters for a Write Timing 8.2 AC Parameters for a Read Timing 9. Mode Register Set 10. Power on Sequence and Auto Refresh (CBR) 11. Clock Suspension (using CKE) 11. 1 Clock Suspension During Burst Read CAS Latency = 2 11. 2 Clock Suspension During Burst Read CAS Latency = 3 11. 3 Clock Suspension During Burst Write CAS Latency = 2 11. 4 Clock Suspension During Burst Write CAS Latency = 3 12. Power Down Mode and Clock Suspend 13. Self Refresh ( Entry and Exit ) 14. Auto Refresh ( CBR ) 15. Random Column Read ( Page within same Bank) 15.1 CAS Latency = 2 15.2 CAS Latency = 3 16. Random Column Write ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Row Read ( Interleaving Banks) with Precharge 17.1 CAS Latency = 2 17.2 CAS Latency = 3 18. Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst INFINEON Technologies AG 19 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 1. Bank Activate Command Cycle (CAS latency = 3) T0 CLK T1 T T T T T Address Bank B Row Addr. Bank B Col. Addr. Bank A Row Addr. Bank B Row Addr. t RCD Command Bank B Activate t RRD NOP Write B with Auto Precharge NOP Bank A Activate NOP Bank B Activate t RC "H" or "L" SPT03784 2. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 Command Read A NOP NOP NOP NOP NOP NOP NOP NOP CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 SPT03712 INFINEON Technologies AG 20 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 3. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 Command Read A Read B NOP NOP NOP NOP NOP NOP NOP CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 SPT03713 4. Read to Write Interval 4.1 Read to Write Interval (Burst Length = 4, CAS latency = 3) T0 CLK Minimum delay between the Read and Write Commands = 4 + 1 = 5 cycles DQMx t DQZ Command NOP Read A NOP NOP NOP NOP Write B NOP NOP Write latency t DQW of DQMx T1 T2 T3 T4 T5 T6 T7 T8 DQ's DOUT A0 DIN B0 DIN B1 DIN B2 Must be Hi-Z before the Write Command "H" or "L" SPT03787 INFINEON Technologies AG 21 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 4. 2 Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 DQM t DQZ t DQW 1 Clk Interval Command NOP NOP Bank A Activate NOP Read A Write A NOP NOP NOP CAS latency = 2 t CK2 , DQ's Must be Hi-Z before the Write Command DIN A0 DIN A1 DIN A2 DIN A3 "H" or "L" SPT03939 4. 3. Non-Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 DQM t DQZ Command NOP Read A NOP NOP Read A NOP t DQW Write B NOP NOP CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's "H" or "L" Must be Hi-Z before the Write Command DOUT A0 DOUT A1 DIN B0 DIN B1 DIN B2 DOUT A0 DIN B0 DIN B1 DIN B2 SPT03940 INFINEON Technologies AG 22 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 5. Burst Write Operation (Burst Length = 4, CAS latency = 2, 3) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 Command NOP Write A NOP NOP NOP NOP NOP NOP NOP DQ's DIN A0 DIN A1 DIN A2 DIN A3 don't care The first data element and the Write are registered on the same clock edge. Extra data is ignored after termination of a Burst. SPT03790 INFINEON Technologies AG 23 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 6. Write and Read Interrupt 6.1 Write Interrupted by a Write (Burst Length = 4, CAS latency = 2, 3) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 Command NOP Write A Write B NOP NOP NOP NOP NOP NOP 1 Clk Interval DQ's DIN A0 DIN B0 DIN B1 DIN B2 DIN B3 SPT03791 6.2 Write Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 Command NOP Write A Read B NOP NOP NOP NOP NOP NOP CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's DIN A0 don't care DOUT B0 DOUT B1 DOUT B2 DOUT B3 DIN A0 don't care don't care DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention. SPT03719 Input data for the Write is ignored. INFINEON Technologies AG 24 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 7. Burst Write and Read with Auto Precharge 7.1 Burst Write with Auto-Precharge (Burst Length = 2, CAS latency = 2, 3 ) T0 CLK CAS Latency = 2: T1 T2 T3 T4 T5 T6 T7 T8 C o m m an d Bank A A ctive NOP W rite A Auto Precharge NOP NOP tWR NOP NOP t RP A ctiva te NOP D Q 's CAS Latency = 3: D IN A 0 D IN A 1 * NOP tWR C o m m a nd Bank A A c tive NOP NOP W rite A Auto Precharge NOP NOP NOP t RP NOP A ctiva te D Q 's D IN A 0 D IN A 1 * * B eg in A u to P re ch arge B a nk ca n b e re activa ted a fte r trp S P T0 3 9 0 9 _ 2 7.2 Burst Read with Auto-Precharge (B u rst L en g th = 4 , C A S la te n cy = 2, 3 ) T0 C LK T1 T2 T3 T4 T5 T6 T7 T8 C om m and Read A w ith A P NOP NOP NOP NOP NOP NOP t RP NOP NOP CAS la te n cy = 2 D Q 's CAS la te n cy = 3 D Q 's * DOUT A0 DOUT A1 DOUT A2 DOUT A3 * DOUT A0 DOUT A1 DOUT A2 t RP DOUT A3 * B e g in A u to P re c h a rg e B a n k ca n b e re a ctiv a te d a fte r trp S P T0 37 2 1_ 2 INFINEON Technologies AG 25 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 8. AC Parameters 8.1 AC Parameters for a Write Timing B u rs t L e ng th = 4, C A S L a te nc y = 2 T0 C LK t CH t CL t CK2 T1 T2 T3 T4 T5 T6 T7 T8 T9 T1 0 T 11 T 1 2 T 13 T 1 4 T1 5 T 16 T 1 7 T1 8 T 19 T 2 0 T2 1 T 2 2 CKE t CKS t CS t CH B e gin A u to P re c h arge B ank A B e g in A u to P re c h arg e Bank B t CKH CS RAS CAS WE BS t AH AP t AS A d dr. RAx CAx RBx CBx RAy RAy RAz RBy RAx RBx RAy RAz RBy DQM t RCD t RC H i-Z DQ A x 0 A x 1 A x2 A x 3 B x 0 B x1 B x2 Bx3 t WR t RP t DS t DH t WR t RP t RRD Ay0 Ay1 A y2 Ay3 A ctiv a te Com m and Bank A A c tiv a te Com m and Bank B W rite w ith A uto P rec h a rg e Com m and Bank B A c tiv a te W rite Com m and Com m and Bank A Bank A P re c ha rg e A ctiv a te A c tiv a te C o m m an d C o m m an d C o m m an d Bank A Bank A Bank B W rite w ith A u to P re c h arge Com m and B a nk A SPT03910_2 INFINEON Technologies AG 26 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 8.2 AC Parameters for a Read Timing Burst Length = 2, CAS Latency = 2 T0 CLK t CH t CL CKE t CKS t CH CS RAS CAS WE BS t AH AP t AS Addr. RAx CAx t RRD t RAS DQM t AC2 t LZ t RCD DQ Hi-Z t OH t AC2 t HZ Ax1 Bx0 Bx1 t RC RBx RBx RAy RAx RBx RAy t CS t CK2 t CKH Begin Auto Precharge Bank B T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 t HZ t RP Ax0 Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Precharge Command Bank A Activate Command Bank A S P T 03911 _2 INFINEON Technologies AG 27 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 9. Mode Register Set C A S L aten cy = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T1 2 T 1 3 T 14 T1 5 T1 6 T 1 7 T 18 T1 9 T 2 0 T 2 1 T 22 CLK CKE t RSC CS RAS CAS WE BS AP A d d re ss K ey Addr. P rec ha rg e C o m m an d A ll B a nk s A ny C o m m an d M od e R eg is te r S et C om m a nd SPT03912_2 INFINEON Technologies AG 28 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 10. Power on Sequence and Auto Refresh (CBR) T0 ~ ~ T1 T2 T3 T4 T5 T6 T7 T8 ~ ~ T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK ~ ~ CKE High Level is required ~ ~ ~ ~ Minimum of 8 Refresh Cycles are required ~ ~ 2 Clock min. CS RAS CAS WE BS AP ~ ~ ~ ~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ Address Key ~~ ~~ ~~ ~~ Addr. DQM ~ ~ t RP DQ ~ ~ ~ ~ ~ ~ t RC Hi-Z Precharge Command All Banks Inputs must be stable for 200 s 1st Auto Refresh Command 8th Auto Refresh Command Mode Register Set Command Any Command SPT03913 INFINEON Technologies AG 29 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 11. Clock Suspension (Using CKE) 11.1 Clock Suspension During Burst Read CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM t CSL t CSL DQ Hi-Z Ax0 Ax1 Ax2 t CSL Ax3 t HZ RAx RAx CAx T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Activate Read Command Command Bank A Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles SPT03914 INFINEON Technologies AG 30 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 11.2 Clock Suspension During Burst Read CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. DQM RAx RAx CAx T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t CSL t CSL t CSL t HZ DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles SPT03915 INFINEON Technologies AG 31 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 11.3 Clock Suspension During Burst Write CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 RAx RAx CAx T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Activate Command Bank A Clock Suspend 1 Cycle Write Command Bank A Clock Suspend 2 Cycles Clock Suspend 3 Cycles SPT03916 INFINEON Technologies AG 32 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 11.4 Clock Suspension During Burst Write3 Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BA A8/AP Addr. DQMx DQ Hi-Z DAx0 DAx1 DAx2 DAx3 RAx RAx CAx T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Activate Command Bank A Clock Suspend 1 Cycle Write Command Bank A Clock Suspend 2 Cycles Clock Suspend 3 Cycles SPT03917 INFINEON Technologies AG 33 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 12. Power Down Mode and Clock Suspend Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM t HZ DQ Hi-Z Ax0 Ax1 Ax2 Ax3 RAx RAx CAx T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t CKS t CKS Activate Command Bank A Active Standby Read Command Bank A Clock Mask Start Clock Mask End Precharge Command Bank A Precharge Standby Any Command Clock Suspend Mode Entry Clock Suspend Mode Exit Power Down Mode Entry Power Down Mode Exit SPT03918 INFINEON Technologies AG 34 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 13. Self Refresh (Entry and Exit) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ ~ ~ CKE ~ ~ t CKS t CKS ~ ~ CS ~ ~ ~ ~ RAS ~ ~ ~ ~ CAS ~ ~ ~ ~ WE ~ ~ ~ ~ BS ~~ ~~ AP ~ ~ ~ ~ Addr. ~ ~ tSREX t RC DQM ~ ~ Hi-Z DQ ~ ~ Begin Self Refresh Exit Command Self Refresh Exit Command issued (async.) SPT03919-3 All Banks must be idle Self Refresh Entry Any Command INFINEON Technologies AG 35 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 14. Auto Refresh (CBR) B u rst L ength = 4, C A S Latency = 2 T0 C LK t CK2 CKE T1 T2 T3 T4 T5 T6 T7 T8 T9 T 1 0 T 1 1 T 12 T 13 T 14 T 15 T 1 6 T 17 T 18 T 19 T 20 T 21 T 22 CS RAS CAS WE BS RAx AP A ddr. t RC t RP DQM H i-Z DQ (M inim um Inte rval) t RC RAx CAx A x0 A x1 A x 2 A x3 P recharge A uto R efresh C om m and C o m m and A ll B anks A uto R efres h C om m a nd A ctivate C om m a nd B ank A R ead C o m m and B ank A SPT03920_2 INFINEON Technologies AG 36 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 15. Random Column Read (Page within same Bank) 15.1 CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3 RAw RAw CAw CAx CAy RAz RAz CAz T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Activate Command Bank A Read Command Bank A Read Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A SPT03921 INFINEON Technologies AG 37 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 15.2 CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 RAw RAw CAw CAx CAy RAz RAz CAz T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Activate Command Bank A Read Command Bank A Read Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A SPT03922 INFINEON Technologies AG 38 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 16. Random Column write (Page within same Bank) 16.1 CAS Latency = 2 B u rs t L en g th = 4 , C A S L a te n c y = 2 T0 C LK t CK2 CKE T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 1 1 T1 2 T 1 3 T 1 4 T 15 T 1 6 T 1 7 T 1 8 T 1 9 T 2 0 T21 T22 CS RAS CAS WE BS AP RBw RBz A d d r. RBw CBw CBx CBy RBz CBz DQM Hi Z DQ DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3 A c tiv a te W rite C o m m a n d C om m a n d B ank B Bank B W rite W rite C om m and C om m and B ank B B a nk B P re c h a rg e A c tiv a te R ead C o m m a n d C o m m an d C o m m a n d B ank B B ank B B ank B SPT03923_2 INFINEON Technologies AG 39 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 16.2. CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 RBz RBz CBz CBx CBy RBz RBz CBz T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank B Precharge Command Bank B Activate Command Bank B Write Command Bank B SPT03924 INFINEON Technologies AG 40 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 17. Random Row Read (Interleaving Banks) with Precharge 17.1 CAS Latency = 2 B u rst L e n g th = 8 , C A S L a te n c y = 2 T0 C LK t CK2 CKE H ig h T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CS RAS CAS WE BS AP RBx RAx RBy A d d r. RBx CBx RAx CAx RBy CBy t RCD DQM t AC2 H i-Z DQ t RP B x0 B x1 B x2 B x3 B x4 B x5 B x6 B x7 A x0 A x1 A x2 A x3 A x4 A x5 A x6 A x7 B y0 B y1 A ctiva te R ead C om m and C om m and B ank B B ank B A ctiva te C om m and B ank A P re c h a rg e A ctiva te C om m and C om m and B ank B B ank B R ead C om m and B ank A R ead C om m and B ank B SPT03925_2 INFINEON Technologies AG 41 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 17.2 CAS Latency = 3 Burst Length = 8, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. RBx RBx CBx RAx RAx CAx RBy RBy CBy T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 High t RCD DQM DQ Hi-Z t AC3 t RP Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 Activate Command Bank B Read Command Bank B Activate Command Bank A Read Command Bank A Precharge Command Bank B Activate Command Bank B Read Command Bank B Precharge Command Bank A SPT03926 INFINEON Technologies AG 42 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 18. Random Row Write (Interleaving Banks) with Precharge 18.1 CAS Latency = 2 B u rs t L e n g th = 8 , C A S L a te n c y = 2 T0 C LK t CK2 CKE H ig h T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CS RAS CAS WE BS AP RAx RBx RAy A d d r. RAx CAx RBx CBx RAy CAy t RCD DQM H i-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 t WR t RP t WR DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 A c tiv a te W rite C om m and C om m and B ank A B ank A A c tiv a te W rite C om m and C om m and B ank B B ank B P re c h a rg e C om m and B ank A A c tiv a te C om m and B ank A P re c h a rg e C om m and B ank B W rite C om m and B ank A SPT03927_2 INFINEON Technologies AG 43 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 18.2 CAS Latency = 3 Burst Length = 8, CAS Latency = 3 T0 CLK t CK3 CKE CS RAS CAS WE BS AP Addr. RAx RAx CAx RBx RBx CBx RAy RAy CAy T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 High t RCD DQM DQ Hi-Z t WR t RP t WR DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B SPT03928 INFINEON Technologies AG 44 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 19. Precharge termination of a Burst 19.1 CAS Latency = 2 Burst Length = 8 or Full Page, CAS Latency = 2 T0 CLK t CK2 CKE CS RAS CAS WE BS AP Addr. RAx RAx CAx RAy RAy CAy RAz RAz CAz T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 High t RP DQM t RP t RP DQ Hi Z DAx0 DAx1 DAx2 DAx3 Ay0 Ay1 Ay2 Az0 Az1 Az2 Activate Command Bank A Write Command Bank A Precharge Termination of a Write Burst. Write Data is masked. Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Precharge Termination of a Read Burst. SPT03933 INFINEON Technologies AG 45 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Package Outline 1 Plastic Package, P-TFBGA-54-2 (8 x 12 mm2, 0.8 mm ball pitch, 3 depopulated rows) Thin Fine pitch Ball Grid Array, SMD tolerance 0.1mm for length and width INFINEON Technologies AG 46 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Package Outline 2 Plastic Package, P-TSOPII-54 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD 0.10.05 155 10.160.13 2) 10.05 0.8 155 3) 0.35 +0.1 -0.05 0.15 +0.06 -0.03 0.5 0.1 11.76 0.2 26x 0.8 = 20.8 0.1 54x 0.2 M 54x 54 28 6 max 1 2.5 max 22.220.13 Index Marking 1) 2) 1) 27 GPX09039 Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side INFINEON Technologies AG 47 2002-12-20 HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Change History Release Date Change Details 2001-08-23 2001-09-24 First Revision Introduced max. package height AC timing tests are referenced to the 0.9V crossover point Package outline defined: 8mm x 12mm Adjusted currents Availability of TSOP package included Jedec conforming package drawings included tRCD and tRP for -7.5 changed header lines: common paragraph format applied (bookmark in PDF) p. 4 and p.6: corrected chip organisation "16Mb x 16" p. 8: Table Operation Definition extended by twp rows "Clock Suspend Entry" and "Clock Suspend Exit" (see mode description on p. 12) p. 8 Note 5 extended by "When this command is asserted during a burst cycle the device enters Clock Suspend Mode." p. 12: "Self Refresh" description improved p. 14: "Absolute Recommended Ratings" for VIN, VOUT, VDD, VDDQ extended p. 14: extended voltage range for VDD and VDDQ = [2.7V, 3.6V] p. 14ff: deleted VDD and VDDQ range above tables and partly replaced by note "(Recommended Operating Conditions unless otherwise noted)" p. 14: VIH,MIN and VOH,MIN redefined p. 14: note 2 clear wording for over- and undershoot as originally intended p. 15: table operating currents updated, symbols changed from ICC to IDD, value type "max." added, IDD6 named "self refresh current" p. 15: IDD1 description ("activate precharge cycles with one bank") updated p. 15: tCK defined by Note 3 or set to infinity p. 15: Note 3 corrected to "... at 133 MHz for -7.5 ..." and partly deleted (formula for IDD(tCK) incorrect) p. 15: Note 4: "assumed" replaced by "used" p. 16: table AC characteristics: clock frequency fCK instead of tCK, CL index 2 and 3 for tCK and tAC, unit CLK replaced by tCK p. 18: PC133 replaced by -7.5 p. 35: revised timing diagram SPT03919-3 p. 46: TFBGA package outline moved to end of data sheet p. 46: TFBGA outline now eps format, added "tolerance 0.1mm for length and width" p. 47: TSOP package outline moved to end of data sheet 2001-11-23 2002-12-20 INFINEON Technologies AG 48 2002-12-20 |
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